Memory Map - Page 255


                       Issue 5

 *ISSUE 2 : Add detailed serial chip data
 *ISSUE 3 : Correct fault in serial chip data
            Improve PIA defs
 *ISSUE 4 : Add disk controller chip description.
 *ISSUE 5 : Improve description of disk status register
            Minor error corrections.

 I/O Memory - $FF00-$FF5F (65280-65375)

       Dec           Hex       Description
    PIA 0 MC6821

    65280           FF00       PIA0 A side data direction  
                               register:these are set to 0
                               so data lines are all inputs.

                               PIA0 A side data lines:
                               BITS:
                               0-6 - keyboard rows 0 to 6
                               0 - right joystick fire
                               1 - left joystick fire
                               7 - joystick comparison input
    65281           FF01       PIA0 A side control register
                               BITS:
                               0 - 0:disable IRQ
                                   1:enable IRQ (0) 
                               1 - control line 1:
                                   0:IRQ on HI to LO
                                   1:IRQ on LO to HI
                               2 - 0:$FF00 is DDR
                                   1:$FF00 is data lines
                               3 - control line 2:
                                   0:control line 2 LO
                                   1:control line 2 HI
                               4 - Control line 2 (CA2)
                                   set by bit 3 (1)
                               5 - CA2 is an o/p = 1
                               6 - IRQ 2 flag(not used)
                               7 - IRQ 1 flag
      Control line 1 connected to:horizontal sync interrupt
      Control line 2 connected to:LSB of two analog 
                               multiplexor select lines.
    65282           FF02       PIA0 B side DDR:All bits set 
                               to 1 so data lines are output

                               PIA0 B side data lines
                               BITS:0-7 keyboard matrix 
                                    columns 0-7
                                    or
                                    0-7 printer data lines
    65283           FF03       PIA0 B side control register
                               BITS:
                               0 - 0:disable IRQ
                                   1:enable IRQ (1)
                               1 - Control line 1:
                                   0:IRQ on HI to LO
                                   1:IRQ on LO to HI
                               2 - 0:$FF02 is DDR
                                   1:$FF02 is data lines
                               3 - Control line 2:
                                   0:line is LO
                                   1:line is HI
                               4 - CB2 is set by bit 3 (1)
                               5 - CB2 is an output=1
                               6 - IRQ2 flag(not used)
                               7 - IRQ flag

     Control line 1 connected to:field sync interrupt
                               (20ms,50Hz)
     Control line 2 connected to:MSB of analog multiplexor
                           select lines.

    Above configurations echoed over memory:
      $FF00-$FF1F (65280-65311)

    EXCEPT:Dragon 64

    R6551  ACIA

    65284           FF04      Transmit data(on write cycle)
                              Recieve data(on read cycle)
    65285           FF05      Status register
                              BITS:
                              0 - 0:No parity
                                  1:Parity Error
                              1 - 0:No framing error
                                  1:Framing Error
                              2 - 0:No overrun
                                  1:Overrun
                              3 - 0:RX data reg empty
                                  1:RX data reg full
                              4 - 0:TX data reg full
                                  1:TX data reg empty
                              5 - 0:DCD high (N/A)
                                  1:DCD low (N/A)
                              6 - 0:DSR high (N/A)
                                  1:DSR low (N/A)
                              7 - 0:No IRQ occurred
                                  1:IRQ has occurred

    65286           FF06      Command register
                              BITS:
                              0 - 0:DTR low (-12V)
                                  1:DTR high (+12V)
                              1 - 0:IRQ enabled
                                  1:IRQ disabled
                              2 - 0:TX IRQ disabled
                                  1:TX IRQ enabled (bit3 
                                    must be 0 else disabled)
                              3 - 0:see bit 2
                                  1:TX IRQ disabled transmit
                                    BREAK on TXD if bit 2=1
                              4 - 0:Reciever normal mode
                                  1:Reciever in echo mode
                                    (bits 2 & 3=0)
                              5 - 0:No parity
                                  1:Parity enabled
                              6 - (bit 7=0)
                                  0:Odd parity
                                  1:Even parity
                                  (bit 7=1)
                                  0:Mark bit sent(check dis)
                                  1:Space bit sent( "     ")

    65287           FF07      Control register
                              BITS:
                              3 2 1 0  Baud Rate Select
                              (for full list see data sheet)
                              0 1 1 0  300
                              0 1 1 1  600
                              1 0 0 0  1200
                              1 0 1 0  2400
                              1 0 1 1  3600
                              1 1 0 0  4800
                              1 1 1 0  9600
                              4 - 0:External clock(N/A)
                                  1:Internal clock
                              5 - (bit6=0)
                                  0:WL=8 data bits
                                  1:WL=7 data bits
                                  (bit6=1)
                                  0:WL=6 data bits
                                  1:WL=5 data bits
                              7 - 0:1 stop bit
                                  1:2 stop bits
                                    1.5 stop bits
                                    (WL=5 & no parity)
                                    1 stop bit
                                    (WL=8 and parity)


    Both 32 & 64

    PIA1  MC6821


    65312           FF20      PIA 1 A side DDR register
                              Bit 0:0 so input
                              Bits 1-7:1 so output

                              PIA 1 A side data lines:
                              BITS:
                              0:cassette data bit input
                              1:printer STROBE line
                              2-7:DAC 6 bit input value
    65313           FF21      PIA 1 A side control register
                              BITS:
                              0 - 0:disable FIRQ
                                  1:enable FIRQ (0)
                              1 - control line 1:
                                  0:FIRQ on HI to LO
                                  1:FIRQ on LO to HI
                              2 - 0:$FF20 is DDR
                                  1:$FF20 is data lines
                              3 - control line 2:
                                  0:line is LO
                                  1:line is HI
                              4 - CA1 is set by bit 3 (1)
                              5 - CA1 is an o/p = 1
                              6 - IRQ2 flag(not used)
                              7 - FIRQ flag

      Control line 1 connected to:printer ACKnowledge line
                                (not used)
      Control line 2 connected to:cassette motor relay:
                                  0 - off
                                  1 - on

     65314          FF22      PIA 1 B side DDR
                              BITS:
                              0-2:0 so inputs
                              (except D64 where 2:1 so out)
                              3-7:1 so outputs
     
                              PIA 1 B side data lines
                              BITS:
                              0 - printer BUSY input
                              1 - single bit sound
                              2 - RAM type:
                                  D32:0:RAM is 32K or 64K
                                      1:RAM is 16K type
                                  D64:0:64K mode BASIC ROM
                                      1:32K mode BASIC ROM
                              3-7 VDG control lines:
                              3 - CSS select between 2 color
                                      sets
                              4-6 Select graphics mode
                              7 - A/G 0:alphanumeric
                                      1:graphic

     65315          FF23      PIA 1 B side control registar
                              BITS:
                              0 - 0:disable FIRQ
                                  1:enable FIRQ (0)
                              1 - control line 1:
                                  0:FIRQ on HI to LO
                                  1-FIRQ on LO to HI
                              2 - 0:$FF22 is DDR
                                  1:$FF22 is data lines
                              3 - control line 2:
                                  0:line is LO
                                  1:line is HI
                              4 - CB1 is set by bit 3 = 1
                              5 - CB1 is an output = 1
                              6 - IRQ2 flag(not used)
                              7 - FIRQ flag

     Control line 1 connected to:CART line of catridge port
     Control line 2 connected to:Sound source enable line on
                                  cartridge port

     Above configurations echoed over memory:
     $FF20-$FF3F (65312-65343)


     65344-65375    FF40-FF5F Cartridge expansion port.

      WD2797 disk controller:

    During disk operations, FIRQs are enabled on PIA1 
    through the CART line, all other interrupt sources are 
    disabled (except ACIA which MUST be done by the user if 
    interrupts have been enabled). The WD2797 causes an FIRQ 
    after every byte transferred, and an NMI when the 
    operation is complete.

     65344          FF40      Command (write) & status 
                              (read) registers.
          Command bytes:

          7 6 5 4 3 2 1 0  Command

          0 0 0 0 x x x x  Restore to track 0
          0 0 0 1 x x x x  Seek
          0 0 1 x x x x x  Step
          0 1 0 x x x x x  Step in
          0 1 1 x x x x x  Step out
                              Bits:
                              4 - 0:No update of track reg
                                  1:Update track register
                              3 - 0:Unload head at start
                                  1:Load head at start
                              2 - 0:No verify of track no
                                  1:Verify track no. on disc
                              1-0 Read as 2 bit stepping 
                              rate:
                                00 = 6ms
                                01 = 12ms
                                10 = 20ms
                                11 = 30ms

          7 6 5 4 3 2 1 0  Command

          1 0 0 x x x x 0  Read sector
          1 0 1 x x x x x  Write sector
          1 1 0 0 0 x x 0  Read address 
          1 1 1 0 0 x x 0  Read track
          1 1 1 1 0 x x 0  Write track

                              Bits:
                              4 - 0:Read/write 1 sector
                                  1:Read all sectors till 
                              the end of a track.
                              3 - Interpretation of 2 bit 
                              sector length field in sector 
                              header:
                                  0: Field is interpreted as
                                     00 = 256 bytes/sector
                                     01 = 512 bytes/sector
                                     10 = 1024 bytes/sector
                                     11 = 128 bytes/sector
                                  1: Field is interpreted as
                                     00 = 128 bytes/sector
                                     01 = 256 bytes/sector
                                     10 = 512 bytes/sector
                                     11 = 1024 bytes/sector
                                  (set to 1 on Dragon)
                              2 - 0:No head loading delay
                                  1:Head loading delay of       
                                  30ms prior to read/writes.
                              1 - 0:Set side select o/p to 0
                                  1:Set side select o/p to 1
                              0 - 0:Write Data Address Mark
                                  1:Write Deleted Data 
                              Address mark

          7 6 5 4 3 2 1 0  Command

          1 1 0 1 x x x x  Force Interrupt

          Generate an interrupt & terminate the current 
          operation on:
                              Bits set:
                              0 - Drive status transition 
                              Not-Ready to Ready
                              1 - Drive status transition 
                              Ready to Not-Ready
                              2 - Index pulse
                              3 - Immediate interrupt

                              Bits clear:
                              No interrupt occurs, all 
                              operations terminated. ($D0)

                              Status (read), when set:

                              Status bits may have different 
                              meanings depending on the 
                              driver operation being 
                              performed.

                              0 - Drive busy
                              1 - Data Request (Data
                                  Read/Data Written) 
                                  OR Index Pulse
                              2 - Lost Data/Track 00
                              3 - CRC error
                              4 - Record Not Found/Seek Err
                              5 - Data Address Mark
                                  0:Data Address Mark read
                                  1:Deleted Data Addres Mark
                                    read
                                  OR Head Loaded
                              6 - Write Protect
                              7 - Not Ready

     65345          FF41      Track register
                              Contains track to seek to.

     65346          FF42      Sector register
                              Contains sector to read/write
     65347          FF43      Data register.
                              Contains data byte just read 
                              or written.
     65352          FF48      Drive select latch
                              Bits:
                              0 - Read as a 2 bit
                              1 - number to select the 
                              required drive (0-3).
                              2 - Enables the drive 
                              selection & turns the disk 
                              motors on.
                              3 - Double/Single density 
                              select (1=single).
                              4 - Enable write 
                              precompensation.
                              5 - Enable NMI interrupt 
                              generation.
                              6-7 unused.